RPDEVS Abstract Simulator

An abstract discrete-event simulator considering input with uncertainty

A timeline in Discrete-Event Simulation (DES) is a sequence of events defined in a numerable subset of R+. Discrete-Event Modeling and Simulation try to reproduce the behaviour of real-world experiments. Nevertheless, measuring the experimental data for science and engineering (which is later used for modeling and simulation) introduces the need for uncertainty quantifications. In modeling of C...

Formal Definition of an Abstract Vhdl'93 Simulator by Eaamachines

We present a rigorous but transparent semantic deenition for VHDL corresponding to the IEEE VHDL'93 standard. Our deenition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our speciication deenes an...

Abstract Cycle Domain Simulator for Phase-Locked Loops

Cycle Domain Simulator for Phase-Locked Loops Norman James October 1999 As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL’s) for frequency multiplication and phase alignment of the clocks. A computer design environment focuses mainly on digital design. A...

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